1. Field of the Invention
The present invention relates to a transistor architecture and simulation technique for optimizing the transistor architecture. More particularly, the present invention is for an architecture having stacked bipolar transistors for a high power amplifier, and a simulation technique for maximizing the transistor RF power output.
2. Background of the Related Art
Recently, the FCC has made several large commercially available allocations of the bandwidth in the millimeter-wave communication bands, namely the V-band (59-64 GHz), E-bands (71-76 GHz & 81-86 GHz), and the W-band (92-95 GHz). Integrated circuit technology that is both mature and capable of operating at these very high millimeter-wave frequencies is known as III-V based integrated circuit technology. See Federal Communications Commission, “FCC 05-45—WTB Allocations and Service Rules for the 71-76 GHz, 81-86 GHz, and 92-95 GHz Bands,” Rep. FCC 05-45, URL: http://hraunfoss.fcc.gov/edocs_public/attachmatch/FCC-05-45A1.pdf, 2005, the contents of which are hereby incorporated by reference. Until the allocations made by the FCC, use of the millimeter-wave communication bands was limited to those with the defense and aerospace industries. Due to this historically limited use of the millimeter-wave frequencies, III-V based integrated circuit technologies have remained dominant as they fit the low volume requirements of the defense and aerospace industries. However, due to low volume production, they have also remained expensive.
Silicon-based integrated circuit technologies, long dominant in the digital computer industry, have enjoyed inexpensive production costs due to the mass volume of production. The continued advance in the speed of digital computers has advanced a key metric that determines the speed of the silicon-based integrated circuit's transistor, known as the fT/fMAX (frequency of unity gain/maximum frequency of operation). Currently, silicon-based transistors have reached near parity with III-V based integrated circuit technologies in terms of the fT/fMAX metric. While silicon-based integrated circuits are essentially ‘as fast as’ III-V-based integrated circuits, because they are optimized for digital behavior and not analog behavior as III-V-based technologies are, they do not match III-V's in terms of a second key metric: RF output power.
However, with the recent allocations made by the FCC, large research efforts have been undertaken to use commercially available, low cost silicon-based integrated circuit technology for millimeter-wave communications over high cost III-V-based integrated circuit technology. The research efforts focus on the idea that low RF (Radio Frequency) output power of the silicon-based technology could be overcome through creative circuit design, instead of modifying the way silicon-based technology is fabricated. See J. D., Cressler, “SiGe HBT Technology: A New Contender for Si-Based RF and Microwave Circuit Applications,” Microwave Theory and Techniques, IEEE Transactions on, vol. 46, no, 5, pp. 572-589, 1998, the contents of which are hereby incorporated by reference. Coupling creative circuit design to increase the RF output power of the silicon-based integrated circuit's transistors, harnessed with the existing large manufacturing base for silicon and its existing high speed fT/fMAX, transistors, one could create a low-cost alternative to III-V technology ushering in a new era of commercial millimeter-wave communications, imaging, and radar products.
At the heart of any communication, imaging or radar system lies a transmitter and receiver. The transmitter is responsible for taking the information needed for transmission and amplifying it for broadcast. The component internal to all transmitters responsible for the final amplification of the signal for broadcast is known as the power amplifier. Commonly integrated circuit technology is used to implement both the transmitter and receiver. When an integrated circuit technology that incapable of generating large amounts of RF output power to create the transmitter's power amplifier, the transmitter will have a limited distance that it can ‘transmit’ the broadcast signal. Integrated circuit technology contains two main types of internal transistor topologies: FETs (Field Effect Transistors) and BJTs (Bipolar Junction Transistors). In an effort to obtain higher speed integrated circuit transistors, to increasing the fT/fMAX, the transistor can be made smaller, so that the electrons and holes, referred to as the ‘charge carriers’, that carry the signal through the transistor have less distance to travel and are therefore faster. A technique known as process scaling, among other techniques, is typically employed to achieve a smaller, faster transistor, FET devices contain a ‘channel’ that the electrons flow down and that channel can be shortened in the scaling process. BJT devices contain a component known as a base that electrons must travel through to traverse the device, so reducing its width through scaling will increase its fT/fMAX. Scaling in the form of shortening channel length for FETs or base width for BJT devices, to decrease carrier transit time, has a side effect. It reduces the amount of voltage one can safely apply across the transistor (FET or BJT) before it is destroyed or ‘broken-down’. As fT/fMAX is increased from one generation of transistors to the next, the breakdown voltage of the transistor is reduced from one process generation to the next [3]. Reduced breakdown voltages effectively decrease the RF output voltage swing and output impedance of transistors. For a transmitter's power amplifiers made from such devices, this results in reduced RF output power and requires more complex circuitry to allow it to operate in a transmitter/receiver system.
A commonly used technique to increase RF output power is to place transistors in parallel, which increases the output current swing of an amplifier, but reduces the output impedance. This makes input and output impedance matching more difficult for the designer. A less commonly used technique is device stacking; of which cascoding is an example. An original device stacking technique known as the HiVP (High Voltage/High Power) configuration offers a unique approach that not only allows the designer to customize the DC bias of their to amplifier, like a cascode, but increases the output voltage swing, improves efficiency, and raises the output impedance, greatly simplifying matching. Originally implemented in GaAs FETs [4], it has recently been implemented using Silicon FETs [5] and InGaP HBTs [6]. In this work we used the original HiVP architecture, provided a novel biasing technique, and extended it for use with BJTs.